Selectively combining signals to produce desired output signal

ABSTRACT

The present invention provides a mechanism for combining programming signals to provide an output signal, the properties of which depend only on selected properties of the programming signals. An embodiment of the invention includes first and second edge-to-pulse converters. The first edge-to-pulse converter generates an intermediate signal having a width determined by received initiation and termination signals. The second edge-to-pulse converter generates an output signal, responsive to the intermediate signal and the termination signal. The output signal has a width determined by a first edge of the initiation signal and a first edge of the termination signal.

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] The present invention relates to mechanisms for processingdigital data, and in particular to mechanisms for combining signals toprovide consistent output behavior.

[0003] 2. Background Art

[0004] Digital systems often include circuitry that combines two or moresignals to generate a new signal. For example, some communicationsystems encode data using pulse width modulation (PWM) to represent oneor more bits of data in the width of an electronic pulse. One way toproduce such a pulse is to generate a first signal that initiates thepulse and, at a delay determined by the states of one or more bits, togenerate a second signal that terminates the pulse. The initiating andterminating signals (“programming signals”) may be signal transitionssuch as the leading or trailing edges of pulses.

[0005] Because data is encoded in the pulse width, the initiating andterminating signals should generate data pulses with reproduciblewidths. Ideally, the width of the output pulse depends on only selectedproperties of the programming signals, and is substantially independentof other properties of the programming signals. For example, where theselected properties are the leading edges of the programming signals,the resulting pulse should be substantially independent of the width ofeither programming signal. Known circuits for combining signals togenerate a new signal do not guarantee this independence.

[0006]FIG. 1 is a schematic diagram of an edge-to-pulse converter orgenerator 100. A pre-charge transistor 110 is connected in series withtransistors 120 and 130, which perform an AND function for initiatingand terminating signals. For the disclosed circuit, START is aninitiating signal that is asserted when it is in a high voltage state,and_STOP is a terminating signal that is asserted when it is in a lowvoltage state. Pre-charge transistor 110 initializes node N to a highvoltage state when_STOP is low (asserted). An inverter 140 converts thehigh voltage at node N to a low voltage state at output 142. When_STOPgoes high, i.e. when the terminating signal is not asserted, N remainsin the high voltage state as long as START is not asserted, and output142 remains in the low voltage state. Converter 100 may be initializedby this sequence of signals.

[0007] With_STOP deasserted, an output pulse (O_PULSE) is initiated byasserting START. Node N discharges through transistors 120 and 130,driving output 142 to a high voltage state. In this state, node N isexposed to a parasitic capacitance at intermediate node M, betweentransistors 120 and 130. The parasitic capacitance is indicated bycapacitor 150. When_STOP is asserted, i.e. driven low, the path toground through transistor 130 is cut off. Node N is recharged to a highvoltage state through transistor 110 and output 142 goes low,terminating O_PULSE.

[0008] Depending on its width, START may or may not still be assertedwhen_STOP is asserted. As a result, transistor 120 may be open orclosed, and node N may or may not be exposed to parasitic capacitance150 when O_PULSE is terminated. The difference in the capacitance seenby transistor 110 can alter the width of O_PULSE generated at output142. For example, it may cause variations in the trailing edge ofO_PULSE, providing, in effect, unintended modulation of its pulse width.Unintended width modulations can have significant consequences for dataintegrity, particularly at higher frequencies. For example, if thesevariations are significant compared to the differences between pulsewidths representing different bit states, data can be corrupted.

[0009] The edge-to-pulse converter discussed above demonstrates aparticular example of a more common problem that arises whenever signalsare combined to generate an output. That is, the output may depend onproperties of the signals to be combined in ways that are not desired.

[0010] The present invention addresses these and other problemsassociated with combining signals to generate an output.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention may be understood with reference to thefollowing drawings, in which like elements are indicated by likenumbers. These drawings are provided to illustrate selected embodimentsof the present invention and are not intended to limit the scope of theinvention.

[0012]FIG. 1 is a circuit diagram of a conventional edge-to-pulseconverter for generating an output signal from a pair of programmingsignals.

[0013]FIG. 2 is a timing diagram representing the voltage staterelationships between an initiating signal and different terminatingsignals applied to the converter of FIG. 1.

[0014]FIGS. 3A and 3B are block diagrams of two embodiments ofedge-to-pulse converters in accordance with the present invention.

[0015]FIG. 4 is a circuit diagram of one embodiment of the edge-to-pulseconverter of FIG. 3A.

[0016]FIG. 5 is a timing diagram representing the programming signalsgenerated by the edge-to-pulse converter of FIG. 3A.

[0017]FIGS. 6A and 6B are timing diagrams of alternative programmingsignals that may be used to provide consistent data pulse widths forgiven programming signals.

[0018]FIG. 7A is a circuit diagram of one embodiment of a transmitterthat incorporates an edge-to-pulse converter in accordance with thepresent invention.

[0019]FIG. 7B is a circuit diagram of one embodiment of a delay modulethat may be used in the transmitter of FIG. 7A.

DETAILED DESCRIPTION OF THE INVENTION

[0020] The following discussion sets forth numerous specific details toprovide a thorough understanding of the invention. However, those ofordinary skill in the art, having the benefit of this disclosure, willappreciate that the invention may be practiced without these specificdetails. In addition, various well-known methods, procedures,components, and circuits have not been described in detail in order tofocus attention on the features of the present invention.

[0021]FIG. 2 illustrates different combinations of programming signals(START and_STOP) that may be combined to provide a data pulse at output142 of edge-to-pulse converter 100. As described above, START initiatesgeneration of an output pulse (O_PULSE) when it is applied to the gateof transistor 120 (FIG. 1)._STOP_0 through_STOP_3 (generically, “_STOP”)represent programming signals that terminate O_PULSE with one of fourdifferent pulse widths. For example,_STOP_0 -_STOP_3 may represent thefour possible states of a pair of bits to be encoded. The selected_STOPterminates O_PULSE when its leading edge 220 is applied to the gates oftransistors 110 and 130. The resulting width of O_PULSE represents thestate of the bit pair associated with the particular_STOP.

[0022] For_STOP_O, START is in a high voltage state when leading edge220(0) is applied to transistor 130. Consequently, node N is exposed toparasitic capacitance 150 when output 142 transitions from high to low.For_STOP_3, START is in a low voltage state when leading edge 220(3) isapplied to transistor 130. In this case, transistor 120 is already off,due to the low state of START, and node N is isolated from parasiticcapacitance 150 when output 142 transitions from high to low. As aresult, the trailing edge of O_PULSE generated by edge-to-pulseconverter 100 may undergo additional, unintended modulation. The leadingedges of_STOP_1 and_STOP_2 may occur relatively close to trailing edge212 of START. This proximity may introduce additional variations inO_PULSE generated by edge-to-pulse converter 100.

[0023] The variations in width of O_PULSE described above areattributable to an unintended dependence on the width of START. That is,instead of providing consistent transitions responsive to the leadingedges of START and_STOP, converter 100 may provide inconsistent resultsdepending on where the trailing edge of START occurs relative to theleading edge of _STOP. This variability poses problems, particularly forhigh speed communications systems, where differences between widths ofdata pulses representing different bit states may be small. Smallmargins may be washed out by such variability.

[0024]FIG. 3A is a block diagram of one embodiment of an edge-to-pulseconverter 300 in accordance with the present invention. Converter 300includes a first converter 310 having an initiate input 320, a terminateinput 330, and an output 340, and a second converter 350 having aninitiate input 360, a terminate input 370 and an output 380. An initiatesignal (START) and a terminate signal (_STOP) are applied to initiateand terminate inputs 320 and 330, respectively, to generate anintermediate start signal (INT_START). As discussed in greater detailbelow, the width of INT_START is determined by START and_STOP. Inparticular, the trailing edge of INT_START is determined by_STOP and issubject to the unintended modulation described above. However, thetrailing edge of INT_START, by design, does not affect the final signal.

[0025] INT_START and_STOP are applied to initiate input 360 andterminate input 370, respectively, of converter 350. Adjusting thetrailing edge of INT_START responsive to_STOP allows converter 300 toimpose a fixed relationship between INT_START and_STOP. That is,INT_START is driven to a consistent voltage state when_STOP is asserted,regardless of the difference between the leading edges of START and_STOPor the width of START.

[0026]FIG. 4 is a circuit diagram of one embodiment 400 of converter 300in accordance with the present invention. Converter 400 includes firstand second converters 404 and 408. Converter 404 includes a pre-chargetransistor 410, coupled at a node N1 to transistors 420, 430, whichperform an AND operation on START and_STOP. A parasitic capacitance at anode M1, between transistors 420 and 430, is indicated by a capacitor494. The gate of transistor 420 is driven by START and the gates oftransistors 410 and 430 are driven by_STOP. An inverter 440 couples nodeN1 to output 442, at which an intermediate initiation signal, INT_START,is provided. Converter 408 includes transistors 450, 460, 470 andinverter 480 in a configuration similar to that of transistors 410, 420,430 and inverter 440, respectively, of converter 404. Nodes N2 and M2 ofconverter 408 correspond to nodes N1 and M1, respectively, of converter404.

[0027] For the disclosed embodiment of converter 400, transistors 420and 430 are turned on, shorting node N1 to ground if START is asserted(transitions to a high voltage state) while _STOP is deasserted (in ahigh voltage state). In this case, output 442 goes high to generate aleading edge for INT_START. When_STOP is asserted, transistor 430 turnsoff and pre-charge transistor 410 turns on, independent of whether STARTis still asserted, i.e. independent of the width of START. This drivesnode N1 high and output 442 low, terminating INT_START. Consequently,the width of INT_START is determined approximately by the differencebetween the leading edges of START and_STOP. The trailing edge ofINT_START is subject to the same variation described above for theO_PULSE generated by converter 100, but the finite response time ofconverter 404 guarantees that INT_START remains high until after_STOP isasserted. As a result, this variation in the trailing edge of INT_STARTdoes not alter O_PULSE.

[0028] INT_START and_STOP are applied to converter 408 to generateO_PULSE. Because converter 404 guarantees that the trailing edge ofINT_START follows the leading edge of STOP for the disclosed embodimentof converter 400, transistor 460 is always turned on when node N2transitions from low to high in response to assertion of_STOP.Consequently, node N2 sees parasitic capacitance 490, no matter what therelative states of START and_STOP at the initiating and terminatinginputs of converter 400.

[0029]FIG. 5 represents the relative timing of START and INT_STARTgenerated by the disclosed embodiment of converter 400 fordifferent_STOP signals, e.g. for different pulse widths. The edges ofthe initiation and termination signals to which converter 400 respondsare indicated by heavy lines. In each instance, the leading edge of_STOPoccurs while INT_START is in the same state, even though START is indifferent voltage states for the different_STOP signals. For thedisclosed embodiment of converter 300, the different instances of_STOPterminate O_PULSE while INT_START is high. For the circuit of FIG. 4,this means that pre-charge transistor 450 sees the parasitic capacitanceat node M2 as the trailing edge of O_PULSE is generated, regardless ofthe relative state of START when the leading edge of _STOP occurs. Theparticular logic states of the programming signals (START,_STOP) areused for illustration only. The present invention does not depend on theparticular logic state to which the initiating signal is driven or theparticular combination of logic states that initiate and terminate thedata pulse.

[0030] Referring again to FIG. 3A, converter 310 introduces a delay inINT_START relative to START. In effect, converter 310 feeds forwardinformation about_STOP to converter 350. One result of this feed-forwardloop is that the difference between the leading edges of INT_STARTand_STOP, i.e. the width of O_PULSE, will be reduced relative to thedifference between the leading edges of START and_STOP. As long as thisreduction is consistent for all_STOP pulses, it can be accounted forreadily. For other embodiments of the invention, different modificationsof START may be employed to ensure a consistent operation of converter350. For example, feedback from O_PULSE may be used to modify START.Generating INT_START with feedback from O_PULSE may introduce a greaterdelay to the trailing edge of INT_START, because of the delay throughgenerator 350 to O_PULSE. The greater width of the resulting INT_STARTpulse may approach limits imposed by the cycle time of CLK_PULSE.

[0031]FIG. 3B is a block diagram of one embodiment 300′ of a converterthat modifies START using feedback from O_PULSE. For this embodiment,INT_START is terminated responsive to the trailing edge of O_PULSE,which ensures that INT_START remains asserted at least until _STOP isasserted.

[0032] In addition, FIGS. 6A and 6B illustrate alternative schemes forensuring a consistent electrical environment for combining signals. Forexample, FIG. 6A represents an intermediate signal (INT_START2), thewidth of which is greater than the delay between the leading edge ofINT_START2 and the leading edge of the terminating signal thatrepresents the largest pulse width for O_PULSE (_STOP_3). Theintermediate signal, INT_START2, may be generated by circuitry thatduplicates the delay between START and_STOP_3 and terminates INT_START2following this delay. However, this approach employs more complexcircuitry than that disclosed for, e.g., converter 400. Further, ifINT_START2 is too wide, it may limit the cycle time of programmingsignals applied to converter 300.

[0033]FIG. 6B represents an intermediate signal, INT_START3), the widthof which is less than the delay between the leading edge of INT_START3and the leading edge of the terminating signal that represents thenarrowest pulse width for O_PULSE (_STOP_0). The pulse width forINT_START3 may be provided, for example, by terminating the intermediatesignal using a delayed version of START. For this embodiment, the widthof INT_START3 is determined by the delay. This implementation has toaccount for low pass filtering, which could reduce the amplitude of aINT_START3 below a level of reliable detection, as it is transmittedthrough various circuit elements.

[0034]FIG. 7A is a circuit diagram of a transmitter 700 including anedge-to-pulse converter in accordance with the present invention.Transmitter 700 comprises a phase modulator 702, a pulse width modulator706 and an amplitude modulator 708. The disclosed embodiment oftransmitter 700 modulates a clock signal (CLK_PULSE) to encode fouroutbound bits per symbol period. One bit is encoded in the symbol'sphase (phase bit), two bits are encoded in the symbol's width (widthbits) and one bit is encoded in the symbol's amplitude (amplitude bit).Transmitter 700 may be used to generate a differential symbol pulse persymbol period.

[0035] Phase modulator 702 includes a MUX 710 and delay module (DM) 712.MUX 710 receives a delayed version of CLK_PULSE via DM 712 and anundelayed version of CLK_PULSE from input 704. The control input of MUX710 transmits a delayed or undelayed CLK_PULSE responsive to the valueof the phase bit. In general, a phase modulator 702 that encodes p phasebits may select one of 2^(P) versions of CLK_PULSE subject to differentdelays. For the disclosed embodiment, the output of phase modulator 702indicates the leading edge of a symbol and serves as a timing referencefor generation of the trailing edge by width modulator 706. Adelay-matching block (DMB) 714 is provided to offset circuit delays inwidth modulator 706 (such as the delay of MUX 720) which mightdetrimentally impact the width of the symbol. The output of DMB 714 isan initiation signal (START), which is provided to an edge-to-pulseconverter (730(a)) associated with amplitude modulator 708 foradditional processing.

[0036] Width modulator 706 includes DMs 722, 724, 726, 728, and MUX 720to generate a second edge that is delayed relative to the first edge byan amount indicated by the width bits. The delayed second edge forms atermination signal (_STOP) that is input to amplitude modulator 708. Forthe disclosed embodiment of transmitter 700, two bits applied to thecontrol input of MUX 720 select one of four different delays for thesecond edge, which is provided at the output of MUX 720. Inputs a, b, c,and d of MUX 720 sample the input signal, i.e. the leading edge,following its passage through DMs 722, 724, 726, and 728, respectively.If the width bits indicate input c, for example, the second edge outputby MUX 720 is delayed by DM 722 +DM 724 +DM 726 relative to the firstedge.

[0037] Amplitude modulator 708 uses START and_STOP to generate a symbolpulse having a leading edge, a width, and a polarity indicated by thephase, width, and amplitude bits, respectively, provided to transmitter700 for a given symbol period. Amplitude modulator 708 includesedge-to-pulse converters (EPC) 730(a), 730(b) and 730(c) and switches740(a) and 740(b). EPC 730(a) operates with either EPC 730(b) or EPC730(c), depending on the states of switches 740(a) and 740(b), to form aconverter in accordance with the present invention. For example, STARTand_STOP are applied to EPC 730(a) to generate INT_START. INT_STARTand_STOP are routed to EPC 730(b) or 730(c), depending on the state ofan amplitude bit, to generate a differential output signal, D_O_PULSE.For one embodiment of transmitter 700, switches 740 may be AND gates. Onreceipt of INT_START, EPC 730(b) or 730(c) initiates D_O_PULSE, which isterminated on receipt of_STOP. Depending on which pair of EPCs 730 isactivated, a positive or a negative going pulse is provided to theoutput of transmitter 700.

[0038] The programmable delays used in the disclosed phase modulator 702and width modulator 706 are used to provide the reliable, relativetimings of START and_STOP required for high bandwidth communication,such as that provided by transmitter 700. Circuits other than theprogrammable delays, such as MUX 720, are not easily designed to provideconsistent delay performance. For this reason, DMB 714 is used to offsetunwanted delays. The present invention may be used to ensure thatrelative timings are due to the controlled delay elements, not tovariable conditions such as those described above for the circuit ofFIG. 1.

[0039]FIG. 7B is a schematic diagram of one embodiment of a programmabledelay module (DM) 770 that is suitable for use with transmitter 700. Forexample, one or more DMs 770 may be used for any of DMs 712, 722, 724,726 and 728 in the disclosed embodiment of transmitter 700 to introduceprogrammable delays in START and_STOP. DM 770 includes inverters 772(a)and 772(b) that are coupled to reference voltages V₁ and V₂ throughfirst and second transistor sets 774(a), 774(b) and 776(a), 776(b),respectively. Reference voltages V₂ and V₂ may be the digital supplyvoltages in some embodiments. Programming signals, p₁-p_(j) andn₁-n_(k), applied to transistor sets 774(a), 774(b) and 776(a), 776(b),respectively, alter the conductances seen by inverters 772(a) and 722(b)and, consequently, their speeds. Programming signals, p₁-p_(j) andn₁-n_(k), for inverters 772(a) and 772(b) may be provided by a system, auser, or a calibration circuit.

[0040] There has thus been disclosed a mechanism for combiningprogramming signals to provide an output signal, the behavior of whichdepends only on a selected property of the programming signals. Anembodiment of the invention includes a circuit having a first stage anda second stage. The first stage receives an initiating signal and aterminating signal and generates an intermediate initiating signal thathas a specified relationship with the terminating signal. For thedisclosed embodiments, the intermediate signal is in a specified voltagestate when a programming feature, e.g. a leading edge, of theterminating signal is received, regardless of the width of theinitiating signal. The second stage of the circuit combines theintermediate initiating signal and the terminating signal to provide anoutput signal that is independent of the width of the initiating signal.

[0041] The disclosed embodiments have been provided to illustratevarious features of the present invention. Persons skilled in the art ofcircuit design, having the benefit of this disclosure, will recognizevariations and modifications of the disclosed embodiments, which nonethe less fall within the spirit and scope of the appended claims.

We claim:
 1. A circuit comprising: a first edge-to-pulse converterhaving a first input to receive an initiating signal and a second inputto receive a terminating signal, the first edge-to-pulse converter toprovide an intermediate initiating signal at an output; and a secondedge-to-pulse converter having a first input to receive the intermediateinitiating signal and a second input to receive the terminating signal,the second edge-to-pulse converter to provide a pulse having a widthdetermined by a first edge of the intermediate initiating signal and afirst edge of the terminating signal.
 2. The circuit of claim 1, whereineach of the first and second converters performs an AND operation on thesignals applied to its first and second inputs.
 3. The circuit of claim2, wherein the AND operation is performed by first and secondtransistors coupled in series and having a first conductivity type, thegates of the first and second transistors forming the first and secondinputs of the converters.
 4. The circuit of claim 3, wherein each of thefirst and second converters further includes a pre-charge transistorcoupled in series with the first and second transistors, a gate of thepre-charge transistor being coupled to the second input of itsrespective converter.
 5. The circuit of claim 4, wherein the initiatingand terminating signals are start and stop pulses, respectively, and thewidth of the intermediate initiating signal is determined by edges ofthe start and stop pulses.
 6. The circuit of claim 1, wherein a trailingedge of the intermediate initiating signal is determined by a leadingedge of the stop pulse.
 7. The circuit of claim 1, wherein the firstconverter includes first, second and third transistors coupled in seriesbetween first and second reference voltages and an inverter coupled to adrain of the first transistor and the converter output.
 8. The circuitof claim 7, wherein the first input is coupled to a gate of the secondtransistor and the second input is coupled to gates of the first andthird transistors.
 9. A method comprising: initiating an intermediatesignal responsive to detection of an initiating signal; terminating theintermediate signal, responsive to detection of a terminating signal;initiating an output signal, responsive to detection of the intermediatesignal; and terminating the output signal, responsive to detection ofthe terminating signal.
 10. The method of claim 9, wherein initiatingthe intermediate signal comprises initiating the intermediate signalresponsive to a leading edge of the initiating signal.
 11. The method ofclaim 9, wherein terminating the intermediate signal comprisesterminating the intermediate signal responsive to a leading edge of theterminating signal.
 12. The method of claim 11, further comprisinggenerating the terminating signal a selected interval following theinitiating signal, the selected interval corresponding to a desiredwidth of the output signal.
 13. A circuit comprising: a start pulsesource to generate a start pulse having a width; a stop pulse source togenerate a stop pulse having a delay relative to the start pulse,determined by a bit; a first edge-to-pulse converter to generate anintermediate pulse having a width determined by the start pulse and afirst edge of the stop pulse; and a second edge-to-pulse converter togenerate a symbol having a width determined by a first edge of theintermediate pulse and the first edge of the stop pulse
 14. The circuitof claim 13, wherein the first edge-to-pulse converter includes an ANDgate that is driven by the start and stop pulses.
 15. The circuit ofclaim 14, wherein the second edge-to-pulse converter includes an ANDgate that is driven by the intermediate and stop pulses.
 16. The circuitof claim 13, wherein the stop pulse source includes a sequence of delaymodules that may be sampled at selected locations of the sequence toprovide the selected delay.
 17. A method comprising: initiating anintermediate signal, responsive to a first programming signal;initiating an output signal, responsive to the intermediate signal;terminating the output signal, responsive to a second programmingsignal; and terminating the intermediate signal, responsive to an eventassociated with the second programming signal.
 18. The method of claim17, wherein terminating the intermediate signal comprises: detecting aleading edge of the second programming signal; and terminating theintermediate signal responsive to detecting the leading edge of thesecond programming signal.
 19. The method of claim 17, whereinterminating the intermediate signal comprises: detecting a trailing edgeof the output signal; and terminating the intermediate signal responsiveto detecting the trailing edge of the output signal.
 20. The method ofclaim 17, wherein the event associated with the second programmingsignal is expiration of an interval that exceeds a delay between thefirst programming signal and a latest second programming signal, andterminating the intermediate signal comprises terminating theintermediate signal responsive to expiration of the interval.
 21. Themethod of claim 17, wherein the event associated with the secondprogramming signal is expiration of an interval that is less than adelay between the first programming signal and an earliest secondprogramming signal, and terminating the intermediate signal comprisesterminating the intermediate signal responsive to expiration of theinterval.
 22. A circuit comprising: a first module having first input toreceive a first programming signal, a second input to receive aterminate signal, the first module to initiate an intermediate signalresponsive to the first programming signal and to terminate theintermediate signal responsive to the terminate signal; and a secondmodule having a first input to receive the intermediate signal and asecond input to receive a second programming signal, the second moduleto initiate and terminate an output signal, responsive to theintermediate signal and the second programming signal, respectively,wherein the terminate signal for the first module is related to thesecond programming signal.
 23. The circuit of claim 22, wherein theterminate signal for the first module is the second programming signal.24. The circuit of claim 23, wherein the first module terminates theintermediate signal responsive to a leading edge of the secondprogramming signal.
 25. The circuit of claim 22, wherein the terminatesignal for the first module is related to the output signal.
 26. Thecircuit of claim 25, wherein the first module terminates theintermediate signal responsive to a trailing edge of the output signal.